1. Field of the Invention
The present invention relates to interlayer connectors for multi-layer integrated circuits and the like, including high density three-dimensional (3D) memory devices.
2. Description of Related Art
In the manufacturing of high density memory devices, the amount of data per unit area on an integrated circuit can be a critical factor. Thus, as the critical dimensions of the memory devices approach lithographic technology limits, techniques for stacking multiple levels or layers of memory cells have been proposed in order to achieve greater storage density and lower costs per bit.
For example, thin film transistor techniques are applied to charge trapping memory in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
Also, cross-point array techniques have been applied for anti-fuse memory in Johnson et al., “512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells,” IEEE J. of Solid-State Circuits, Vol. 38, No. 11, November 2003. See, also U.S. Pat. No. 7,081,377 to Cleeves entitled “Three-Dimensional Memory.”
Another structure that provides vertical NAND cells in a charge trapping memory technology is described in “Novel 3-D Structure for Ultra-High Density Flash Memory with VRAT and PIPE,” by Kim et al., 2008 Symposium on VLSI Technology Digest of Technical Papers;” 17-19 Jun. 2008; pages 122-123.
In three-dimensional (3D) stacked memory devices, conductive interconnects used to couple the lower layers of memory cells to decoding circuitry and the like pass through the upper layers. The cost to implement the interconnections increases with the number of lithographic steps needed. One approach to reduce the number of lithographic steps is described in Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007; pages 14-15.
Technology is being developed to reduce the number of lithographic mask steps required to establish contacts at each contact level. For example, U.S. Pat. No. 8,598,023 and U.S. Pat. No. 8,383,512 disclose what can be referred to as binary sum systems for forming interlayer connectors extending to the conductive layers of a stack of active layers interleaved with insulating layers. These two just mentioned patents are incorporated by reference as if fully set forth herein. Also, ternary and quaternary sum processes have been developed.
In a binary sum system etch process, M etch masks can be used in the creation of interlayer connectors to 2M active layers. Also, in other examples, M etch masks can be used to create interlayer connectors to NM conductive layers, with N being an integer greater than or equal to 3. Therefore, with N equal to 3, only 3 etch masks are needed to form interlayer connectors to landing areas at 27 conductive layers. This is achieved by etching, trimming the etch mask and etching again using the trimmed etch mask. The selection of N reflects the number of times each etch mask is trimmed with N=3 for one trim step, N=4 for two trim steps, etc. Therefore, there is an initial etch step, a trim step, and an etch step following each trim step. With N=3, the process can be referred to as a ternary system. For example, with a quaternary system, so that N=4 reflecting two trim steps, 3 masks (M=3) can be used to create interlayer connectors to landing areas at 43 or 64 conductive layers, while 4 masks (M=4) can be used to create interlayer connectors to landing areas at 44 or 256 conductive layers.
Other processes to form the required interlayer connectors can also be used. However, limitations can arise as the number of layers increases, because not only does the number of etch steps increase even using binary system etch approaches, but also the depths of the required vias increase. With greater depths, the layout area for each interlayer connector can increase and process control issues arise.
Thus it is desirable to provide a technology that can improve the reliability and reduce the costs of manufacturing for interlayer connectors in multilayer integrated circuts such as 3D memory.